A Delta-Sigma (ΔΣ) modulator removes noise in a signal band of interest so that when the desired signal is received, the dynamic range within the signal band is improved. The dynamic range is measured as the difference between the received signal and noise floor as given in dBm. Removing the noise, or more specifically re-shaping the noise, out of the signal band increases the notch depth which is the same as lowering the noise floor. It is easier to remove the noise for deeper notch characteristics in narrow band applications (˜1 MHz) so a very high dynamic range (100 dB) can then be achieved. Conversely for wider signal bandwidths (˜200 MHz), more shallow notches are obtained which result in less dynamic range (60 dB).
A Delta-Sigma (ΔΣ) modulator is often used as an important part of a Analog to Digital Converter to lower the noise floor for a analog signal of interest. Such an Analog to Digital Converter is commonly called a Delta-Sigma Analog to Digital Converter.
Performance of a Delta-Sigma (ΔΣ) modulator is strongly tied to the clock rate because (i) increasing the ratio of clock rate to signal bandwidth improves dynamic range, and (ii) faster sampling is necessary for bandpass operation at high signal frequencies. Increasing the clock rate, however, imposes even harder design challenges on the quantizers within the modulator. The architecture of the disclosed ΔΣ modulator leverages interleaving concepts to relax the quantizer clock rate (of the internal ADCs and DACs) without changing the effective oversampling ratio, thus, making it easier to reach aggressive dynamic range goals across wider bandwidths at higher frequencies than has been done in the prior art.
Traditional software-based (or software-defined) receiver architectures have extra conversion stages to reduce the Radio Frequencies (RF) down to a frequency that can be supported by a high-resolution ADC. These solutions have added complexity, size, power, and cost to the software-based receiver. Furthermore, traditional hardware based receivers have limited cross-functionality and can only be modified through physical intervention. Thus, the evolution in receiver design has been towards software-based receiver architectures due to their programmability and design efficiency but preferably without sacrificing performance of traditional hardware based receivers. The ΔΣ modulator has emerged as a preferred candidate for the front-end ADC in these software-based receiver architectures. However, attaining a high dynamic range (for example, a dynamic range of 80+ dB) at input signal frequencies (for example, frequencies above 1 GHz) has not yet been achieved.
The ΔΣ modulator architecture disclosed herein interleaves the multi-bit quantizers to maintain a fast effective sampling rate—thus supporting higher frequencies of operation—but the sampling rate of each quantizer is reduced by the interleaving factor thus enabling higher dynamic range performance.
Time-interleaving of two delta-sigma modulators has been published most recently by Chun-Yao Lu, “A High-Resolution Time-Interleaved Delta-Sigma Modulator with Low Oversampling”, Proc. of the International Symposium on Integrated Circuits, (ISIC), December 2009 for use in audio applications. The two modulators are coupled together with additional analog paths for compensation similar to what is shown in FIG. 1(a) which is a simplified representation of the teachings of this prior art. The architecture presented can theoretically reduce the sampling rate by a factor of four and increase the dynamic range when compared to a conventional modulator. However, the prior art approach of this paper is effectively limited to low frequency operation because, in practice, a slight mismatch between the even and odd paths depicted in FIG. 1(a) (and in FIG. 4 of that paper) could dramatically degrade the dynamic range of that modulator.
Another bandpass ΔΣ modulator architecture with partial interleaving has been designed for high-IF operation as taught by Julien Ryckaert et al., “A 6.1 GS/s 52.8 mW 43 dB DR 80 MHz Bandwidth 2.4 GHz RF Bandpass ΔΣ ADC in 40 nm CMOS” IEEE Radio Frequency Integrated Circuits Symposium (RFIC), May 2010. See FIG. 1(b). The ADC in the forward path of the modulator has been interleaved to relax the speed of the clock. The output quantized data is then multiplexed back up to the system data rate for conversion to the analog error signal by a single DAC. The ADC and DAC are not multi-bit quantizers, but rather single bit quantizers, and are limiting the achievable dynamic range for the chosen order of the modulator. An extension of the published architecture to multi-bit levels would not necessarily achieve a commensurate increase in dynamic range since the DAC—non-interleaved and still operating at full clock rate—would limit the overall modulator performance. A pictorial view of the architecture is shown in FIG. 1(b) for comparison with other prior art and with the approach presented herein.
A 1-bit ADC is just a single comparator which drives a 1-bit DAC which is a single switchable current source. A 1-bit DAC is inherently linear and does not introduce non-linearity to the system. Theory shows that every additional bit in the ADC and DAC increases the dynamic range (DR) by 6 dB, however, at some point the non-linearity of a multi-bit DAC becomes an issue so adding more bits does not further increase dynamic range. The basic theory of delta-sigma demonstrates that the RMS noise goes as 2−K where K is the number of quantizer bits. An example of a work covering this basic theory is James C. Candy and Gabor C. Temes, “Oversampling Delta-Sigma Data Converters: Theory, Design, and Simulation, 1st Edition,” 1992, pages 1-16.
Interleaving both the multi-bit ADC and DAC, as proposed herein, is a substantially more difficult problem than that addressed in prior art. Meeting dynamic range goals requires matching among the interleaved DACs in addition to managing mismatch within an individual DAC. Also, interleaving increases the excess phase delay in the loop and therefor compensation is utilized to maintain stability. These challenges are difficult and may make the proposed solution appear infeasible to others but we have identified technical solutions that enable the new architecture.